/*!
 * \file       ny8ae51e.h
 * \brief      NY8AE51E header file
 * \author     HuangTing
 * \date       2020.08-18
 * \details    define register
 */

#ifndef NY8AE51E_H_F7ZRLLXP
#define NY8AE51E_H_F7ZRLLXP

#ifndef __CPU_HAS_SET
#  ifdef __SDCC
#    warning "Use NY8.h instead of <icbody>.h for consistency."
#  endif
#endif

#include <ny8common.h>

#ifndef   __EEPROM_SUPPORTED
#  define __EEPROM_SUPPORTED 1
#endif
#ifndef   __EEPROM_TIMEOUT
#  define __EEPROM_TIMEOUT 1
#endif
#include <ny8_eeprom.h>

//! INDF (Indirect Addressing Register)
extern __at(0x0000) __sfr INDF;

//! TMR0 (Timer0 Register)
extern __at(0x0001) __sfr TMR0;

//! PCL (Low Byte of PC[9:0])
extern __at(0x0002) __sfr PCL;

//! STATUS (Status Register)
extern __at(0x0003) __sfr STATUS;

//! FSR (Register File Selection Register)
extern __at(0x0004) __sfr FSR;

typedef struct __PORTBbits_t
{
    unsigned PB0    : 1;
    unsigned PB1    : 1;
    unsigned PB2    : 1;
    unsigned PB3    : 1;
    unsigned PB4    : 1;
    unsigned PB5    : 1;
    unsigned GP6    : 1;
    unsigned GP7    : 1;
} __PORTBbits_t;

//! PortB (PortB Data Register)
extern __at(0x0006) __sfr                  PORTB;
extern __at(0x0006) volatile __PORTBbits_t PORTBbits;
__sbit PB0 = PORTB : 0;
__sbit PB1 = PORTB : 1;
__sbit PB2 = PORTB : 2;
__sbit PB3 = PORTB : 3;
__sbit PB4 = PORTB : 4;
__sbit PB5 = PORTB : 5;

typedef struct __PCONbits_t
{
    unsigned EELOCK  : 1; //!< Check EEPORM write lock state bit
    unsigned EEW_ERR : 1;
    unsigned GP2     : 1;
    unsigned LVREN   : 1; //!< Enable/disable LVR
    unsigned GP4     : 1;
    unsigned LVDEN   : 1; //!< Enable/disable LVD
    unsigned GP6     : 1;
    unsigned WDTEN   : 1; //!< Enable/disable WDT
} __PCONbits_t;

//! PCON (Power Control Register)
extern __at(0x0008) __sfr                 PCON;
extern __at(0x0008) volatile __PCONbits_t PCONbits;
__sbit EELOCK  = PCON : 0;
__sbit EEW_ERR = PCON : 1;
__sbit LVREN   = PCON : 3;
__sbit LVDEN   = PCON : 5;
__sbit WDTEN   = PCON : 7;

typedef struct __BWUCONbits_t
{
    unsigned WUPB0  : 1;
    unsigned WUPB1  : 1;
    unsigned WUPB2  : 1;
    unsigned WUPB3  : 1;
    unsigned WUPB4  : 1;
    unsigned WUPB5  : 1;
    unsigned        : 1;
    unsigned        : 1;
} __BWUCONbits_t;

//! BWUCON (PortB Wake-up Control Register)
extern __at(0x0009) __sfr                   BWUCON;
extern __at(0x0009) volatile __BWUCONbits_t BWUCONbits;
__sbit WUPB0 = BWUCON : 0;
__sbit WUPB1 = BWUCON : 1;
__sbit WUPB2 = BWUCON : 2;
__sbit WUPB3 = BWUCON : 3;
__sbit WUPB4 = BWUCON : 4;
__sbit WUPB5 = BWUCON : 5;

//! PCHBUF (High Byte of PC)
extern __at(0x000a) __sfr PCHBUF;

typedef struct __BPLCONbits_t
{
    unsigned        : 1;
    unsigned        : 1;
    unsigned        : 1;
    unsigned        : 1;
    unsigned PLPB0  : 1;
    unsigned PLPB1  : 1;
    unsigned PLPB2  : 1;
    unsigned PLPB3  : 1;
} __BPLCONbits_t;

//! BPLCON (PortB Pull-Low Resistor Control Register)
extern __at(0x000b) __sfr                   BPLCON;
extern __at(0x000b) volatile __BPLCONbits_t BPLCONbits;
__sbit PLPB0 = BPLCON : 4;
__sbit PLPB1 = BPLCON : 5;
__sbit PLPB2 = BPLCON : 6;
__sbit PLPB3 = BPLCON : 7;

typedef struct __BPHCONbits_t
{
    unsigned PHPB0  : 1;
    unsigned PHPB1  : 1;
    unsigned PHPB2  : 1;
    unsigned PHPB3  : 1;
    unsigned PHPB4  : 1;
    unsigned PHPB5  : 1;
    unsigned        : 1;
    unsigned        : 1;
} __BPHCONbits_t;

//! BPHCON (PortB Pull-High Resistor Control Register)
extern __at(0x000c) __sfr                   BPHCON;
extern __at(0x000c) volatile __BPHCONbits_t BPHCONbits;
__sbit PHPB0 = BPHCON : 0;
__sbit PHPB1 = BPHCON : 1;
__sbit PHPB2 = BPHCON : 2;
__sbit PHPB3 = BPHCON : 3;
__sbit PHPB4 = BPHCON : 4;
__sbit PHPB5 = BPHCON : 5;

typedef struct __INTEbits_t
{
    unsigned T0IE   : 1; //!< Timer0 overflow interrupt enable bit
    unsigned PBIE   : 1; //!< PortB input change interrupt enable bit
    unsigned INTIE  : 1; //!< External interrupt enable bit
    unsigned T1IE   : 1; //!< Timer1 underflow interrupt enable bit
    unsigned LVDIE  : 1; //!< Low-voltage detector interrupt enable bit
    unsigned        : 1;
    unsigned WDTIE  : 1; //!< WDT timeout interrupt enable bit
    unsigned        : 1;
} __INTEbits_t;

//! INTE (Interrupt Enable Register)
extern __at(0x000e) __sfr                 INTE;
extern __at(0x000e) volatile __INTEbits_t INTEbits;
__sbit T0IE  = INTE : 0;
__sbit PBIE  = INTE : 1;
__sbit INTIE = INTE : 2;
__sbit T1IE  = INTE : 3;
__sbit LVDIE = INTE : 4;
__sbit WDTIE = INTE : 6;

typedef struct __INTFbits_t
{
    unsigned T0IF   : 1; //!< Timer0 overflow interrupt flag bit
    unsigned PBIF   : 1; //!< PortB input change interrupt flag bit
    unsigned INTIF  : 1; //!< External interrupt flag bit
    unsigned T1IF   : 1; //!< Timer1 underflow interrupt flag bit
    unsigned LVDIF  : 1; //!< Low-voltage detector interrupt flag bit
    unsigned        : 1;
    unsigned WDTIF  : 1; //!< WDT timeout interrupt flag bit
    unsigned        : 1;
} __INTFbits_t;

//! INTF (Interrupt Flag Register)
extern __at(0x000f) __sfr                 INTF;
extern __at(0x000f) volatile __INTFbits_t INTFbits;
__sbit T0IF  = INTF : 0;
__sbit PBIF  = INTF : 1;
__sbit INTIF = INTF : 2;
__sbit T1IF  = INTF : 3;
__sbit LVDIF = INTF : 4;
__sbit WDTIF = INTF : 6;

typedef struct __INTE2bits_t
{
    unsigned        : 1;
    unsigned        : 1;
    unsigned        : 1;
    unsigned        : 1;
    unsigned EEWIE  : 1; //!< EEPROM write completion interrupt enable
    unsigned        : 1;
    unsigned        : 1;
    unsigned        : 1;
} __INTE2bits_t;

//! INTE2 (Interrupt enable Register 2)
extern __at(0x0017) __sfr                  INTE2;
extern __at(0x0017) volatile __INTE2bits_t INTE2bits;
__sbit EEWIE = INTE2 : 4;

typedef struct __INTEDGbits_t
{
    unsigned INTG0  : 1; //!< INT edge trigger select bit
    unsigned INTG1  : 1; //!< INT edge trigger select bit
    unsigned        : 1;
    unsigned        : 1;
    unsigned EIS    : 1; //!< External interrupt select bit
    unsigned        : 1;
    unsigned        : 1;
    unsigned        : 1;
} __INTEDGbits_t;

//! INTEDG (Interrupt Edge Register)
extern __at(0x0018) __sfr                   INTEDG;
extern __at(0x0018) volatile __INTEDGbits_t INTEDGbits;
__sbit INTG0 = INTEDG : 0;
__sbit INTG1 = INTEDG : 1;
__sbit EIS   = INTEDG : 4;

//! TMRH (Timer High Byte Register)
extern __at(0x0019) __sfr TMRH;

//! PWM3RH (PWM3DUTY High Byte Register)
extern __at(0x001c) __sfr PWM3RH;

typedef struct __INTF2bits_t
{
    unsigned        : 1;
    unsigned        : 1;
    unsigned        : 1;
    unsigned        : 1;
    unsigned EEWIF  : 1; //!< EEPROM write completion flag bit
    unsigned        : 1;
    unsigned        : 1;
    unsigned        : 1;
} __INTF2bits_t;

//! INTF2 (Interrupt Flag Register 2)
extern __at(0x001f) __sfr                  INTF2;
extern __at(0x001f) volatile __INTF2bits_t INTF2bits;
__sbit EEWIF = INTF2 : 4;

//! IOSTB (PortB I/O Control Register)
extern __at(0x00800006) volatile __fpage IOSTB;

//! PS0CV (Prescaler0 Counter Value Register)
extern __at(0x0080000a) volatile __fpage PS0CV;

//! BODCON (PortB Open-Drain Control Register)
extern __at(0x0080000c) volatile __fpage BODCON;

//! PCON1 (Power Control Register1)
extern __at(0x0080000f) volatile __fpage PCON1;

//! TMR1 (Timer1 Register)
extern __at(0x01000000) volatile __spage TMR1;

//! T1CR1 (Timer1 Control Register1)
extern __at(0x01000001) volatile __spage T1CR1;

//! T1CR2 (Timer1 Control Register2)
extern __at(0x01000002) volatile __spage T1CR2;

//! PWM1DUTY (PWM1 Duty Register)
extern __at(0x01000003) volatile __spage PWM1DUTY;

//! PS1CV (Prescaler1 Counter Value Register)
extern __at(0x01000004) volatile __spage PS1CV;

//! BZ1CR (Buzzer1 Control Register)
extern __at(0x01000005) volatile __spage BZ1CR;

//! IRCR (IR Control Register)
extern __at(0x01000006) volatile __spage IRCR;

//! TBHP (Table Access High Byte Address Pointer Register)
extern __at(0x01000007) volatile __spage TBHP;

//! TBHD (Table Access High Byte Data Register)
extern __at(0x01000008) volatile __spage TBHD;

//! P2CR1 (PWM2 Control Register1)
extern __at(0x0100000a) volatile __spage P2CR1;

//! PWM2DUTY (PWM2 Duty Register)
extern __at(0x0100000c) volatile __spage PWM2DUTY;

//! OSCCR (Oscillation Control Register)
extern __at(0x0100000f) volatile __spage OSCCR;

//! P3CR1 (PWM3 Control Register1)
extern __at(0x01000011) volatile __spage P3CR1;

//! PWM3DUTY (PWM3 Duty Register)
extern __at(0x01000013) volatile __spage PWM3DUTY;

extern __at(0x00800000) volatile __t0mdpage T0MD;

#endif /* end of include guard: NY8AE51E_H_F7ZRLLXP */
